Efficient VLSI Architecture for Edge Sensing Anti-Aliasing Demosaicing

The majority of digital cameras reconstruct full-color images from raw data captured by image sensors through a process called demosaicing. In this paper, we propose an edge sensing anti-aliasing demosaicing (ESAAD) algorithm for the Bayer pattern, which is the most widely used color filter array (CFA) layout, and an efficient very-large-scale integration (VLSI) architecture for hardware implementation of the ESAAD. Traditional demosaicing methods recover the RGB channels of pixels on and not on edges in the same way while ESAAD detects edges from the RAW images and recovers pixels on and not on edges by different strategies. In this way, we can improve the visuality of recovered edges greatly compared with previous demosaicing methods. In addition, the simplicity of the ESAAD enables a hardware-friendly VLSI architecture which only requires 2 lines of line buffers. Under the same conditions of the process technology with 180nm CMOS, the image resolution with 1280×720 (HD), and the working frequency with 200MHz, the performance of this work significantly outperforms all the other methods on resources usage including both gate counts and core area, and power consumption.