A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS

This paper describes a compact analog PLL architecture for low-voltage clock generation systems. The digital PLL (DPLL) suffers from a large variation in the time resolution of a TDC over supply voltage. To achieve robust clock generation with a low supply voltage, a PLL without a charge pump (CP) is proposed for the design of a hybrid PLL. To verify the in-band noise performance of the analog CP-less PLL, a prototype integer-N PLL with a ring VCO is implemented in 14nm FinFET CMOS. The bias-current-free PLL features the compact area of 0.0048mm
²
and the minimum operation voltage of 0.43V, while consuming 1.27mW from a 0.6V supply at 1GHz output.