Design and Implementation of Feedback Cancellation Algorithm for Hearing Aids

This paper presents the optimization idea, hardware implementation architecture and low power optimization process of feedback cancellation algorithm applied in hearing aid chip. Based on the NLMS algorithm, three band limited IIR filters with configurable coefficients are added. Also, the filtered de echo signal is introduced into the calculation of normalized adaptive step factor to solve the biased estimation and distortion problems of NLMS algorithm, so as to realize the accurate adaptation of echo path and echo signal. In the implementation of hardware architecture, the adaptive feedback cancellation module is integrated outside the buffer, and processed point-by-point to reduce the algorithm complexity, hardware implementation resources and power consumption. The solution of double operation unit is further proposed, which improves the efficiency of data processing, and meets the operation requirements at low working frequency. Finally, the MPW chip is verified by SMIC 130nm 1P8M mixed signal CMOS process. Under the working frequency of 4.096MHz, the post simulation power consumption of the module is only 187μW. The chip area is 0.237mm
²
, which fully meets the requirements of low power consumption of hearing aid chip.