Unleashing the computational power of FPGAs to efficiently perform SPMV operation

The sparse matrix vector product (SpMV) is a fundamental operation in multiple scientific algorithms, because it is generally the most computationally expensive stage. For this reason, numerous efforts have been made to optimize such operation on various hardware platforms. There is a growing concern in the high-performance computing world about power consumption, making energy efficiency an extremely important quality when evaluating hardware platforms. Due to their greater energy efficiency, Field-Programmable Gate Arrays (FPGAs) are available today as an interesting alternative to other hardware platforms for the acceleration of this type of operations. Our study focuses on the development of efficient kernels for the resolution of SpMV, measuring the achievable performance with respect to the hardware capabilities. In order to do so, we developed experiments that evaluate the peak performance of our platforms and based on the results we implemented optimized kernels for the calculation of SpMV. The tests were performed on Xilinx’s Alveo U50 platform. Among the results obtained, we highlight the convenience of applying fine-grained parallelism (vectorization of the data path) versus the coarse-grained (replication of the computation unit), achieving improvements in the first case of 7.7× compared to the second. We also observed that, in most cases, the FPGA platform provides higher energy efficiency than a traditional CPU, reaching a maximum of 3×.