Maximizing Switch Allocation Matching to Reduce Latency in Network-on-Chip

Switch Allocation (SA) carries a critical pipeline stage in improving latency in Network-on-Chip (NoC). SA is responsible for assigning flits at the input queue to the output port for sending them to their destination. The allocation specifies the matching between the arriving requests and assigning ports to them. To maximize this matching, a Virtual Channel (VC) router architecture is suggested in this paper. The proposed design enhances the chances of mapping for the packets appearing in SA stage. The proposed architecture is evaluated using cycle accurate tool Booksim. The latency results indicate significant performance improvement of NoC router.