Analysis of Fully-Pipelined CNN Implementation on FPGA and HBM2

Contrasting with conventional DRAM memory, High Bandwidth Memory (HBM2) can expand the bandwidth and improve power consumption. In this study, we use HBM2 for implementing an FPGA-based fully-pipelined convolutional neural network inference accelerator. To efficiently utilize high bandwidth, the output feature maps of each layer in the accelerator are computed row-by-row and immediately feed as input to the next layer. The VGG11 model is deployed on the CIFAR100 dataset to evaluate the performance and energy efficiency of the accelerator. The system is implemented on Xilinx Alveo U280 FPGA. Our experimental results show that the system achieves 111× and 1.7× higher than the Intel i9-10940X CPU and GeForce RTX 3090 GPU in energy efficiency, respectively.