A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM

In order to reduce power consumption of the main memory of computers, the use of MRAM (magnetoresistive random access memory) instead of DRAM is attractive, since MRAM does not require periodic refresh energy while achieving sufficiently small read/write latencies. Among various types of MRAM devices, VC-MRAM (voltage-controlled MRAM) has a great potential to realize massively energy-efficient memory subsystems. Its write energy is 2 times orders of magnitudes smaller than that of STT-MRAM. The problem with VC-MRAM, however, is that its write error rate (i.e., 10
⁻⁴
with today’s typical technologies) is much higher than the acceptable error rate that has been supposed to be required for the main memory (i.e., 10
⁻⁹
). In this paper, we investigate whether such errors derived from an erroneous memory device cause a problem in actual program execution in the memory subsystem with hierarchical cache memory. We develop a memory subsystem simulator that mimics the structure of the multi-level caches and the main memory based on a VC-MRAM model, and observe cell-level operations in the main memory throughout the execution of benchmark programs. From results, we find the number of bit corruptions depends greatly on the cache size and the error model of the device. This is because the number of memory accesses itself can be significantly reduced by passing through the cache. Furthermore, we observe that the occurrences of bit corruptions more than 3 bits that cannot be handled properly by the hamming ECC codes seldom happen. This observation leads us to the insight that VC-MRAM with Hamming ECC can be used as main memory in some applications if these are executed on CPUs with a large cache memory.