Real time HEVC video compression using Hybrid DWT-DCT algorithm on an FPGA

This paper provides an HEVC (High-Efficiency Video Coding) video compression or transcoding using Hybrid algorithm. The hybrid compression technique uses DWT (Discrete Wavelet Transformation) transform as well as that use DCT (discrete cosine transformation) transform.In the existing paper video compression was tested using DCT and DWT. In this paper testing is performed using Hybrid DWT-DCT and there by the input coding is not overlapped by another 2-D blocks. In the proposed work PSNR (Peak Signal to Noise Ratio) value is improved when compared to the existing work.Also, hardware implementation of one frame/image real-time HEVC decoder using Hybrid algorithm results is shown by using a field-programmable gate array (FPGA). Hardware implementation become more appealing due to their superior performance in terms of FPGA latency compared to CPU (Central Processing Unit) latency to execute or implement this Hybrid algorithm. Also, pipelined hybrid decoder architecture is used to absorb variations in processing time. This architecture achieves a target operating frequency of 150 MHz.