A Synthesizable 0.0060mm2 VCO-Based Delta Sigma Modulator with Digital Tri-level Feedback Scheme

A low-power, small-area, and medium-resolution analog-to-digital converter (ADC) is one of the critical building blocks in a system-on-chip (SoC). But it is also a primary bottleneck of SoC time-to-market due to full custom design. To improve design efficiency, the digital synthesis tools are employed to accelerate its layout design as long as the ADC mostly consists of digital standard cells and can be described in Hardware Description Languages (HDLs). This kind of ADC is called as synthesizable ADC [1–2], in which a voltage-controlled oscillator (VCO)-based ADC has become a popular choice because of its high digitization. However, the open-loop VCO-based ADC suffers from the inherent nonlinearity of VCO and necessitates calibration [3]. A closed loop is adopted to suppress the nonlinearity [4], but requires a feedback scheme with a digital-to-analog converter (DAC). A bi-level feedback scheme in the digital style is proposed in [5], but it ignores the lead-lag status between dual VCO. A tri-level feedback scheme is proposed in [6] to make full use of the phase resolution. However, it is designed in the analog style and hard to synthesize due to analog circuitry, including analog switches and reference generators.