Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications

IGZO (InGaZnO)-DRAM has been increasingly explored as an alternative to traditional DRAM due to its reduced transistor leakage (∼10
⁻¹⁸
A) and related minimal storage node capacitance in addition to ease of integration (entirely BEOL). The 2TOC IGZO-DRAM bit-cell configuration has additional benefits from a scaling point of view due to the potential for monolithic 3D stacking. We present a 2TOC IGZO based Capacitor-less memory that enhances the sensing margin and retention time for DRAM applications requiring higher data immunity. In the proposed technique for increased data integrity, the Read Bit-Line (RBL) is precharged at Half-VDD, instead of Full-VDD, to utilize the rising edge of read word line (RWL) at the beginning of read. This increases the storage node potential of the bit-cell (due to coupling between RWL and the storage node) which is otherwise degraded at write termination due to coupling of write word line (WWL) and the storage node. From our simulation results, the proposed scheme (termed as HVPC-RBL) demonstrates stronger data integrity on data ‘1’ without the need for any additional cell capacitor. An additional benefit is the higher SN level (> 2X) resulting in higher sensing speed (10X) allowing reduced parasitic cell capacitance requirement ∼1aF. This is 1000X less than the ∼ 1fF parasitic cell capacitance required at the storage node for the conventional VDD-precharged RBL scheme (VPC-RBL).