Design of a Phase Disposition PWM Technique for Reduced Switch Asymmetric 31-Level Inverter

A challenging task in designing a multi-level inverter is to increase the output voltage level while keep the switching devices, DC voltage sources, and corresponding diodes to a minimum number. In this paper, the analysis, and implementation of a 31-level asymmetric inverter is presented. This shows efficient performance in terms of voltage levels, number of components count, and total harmonic distortion, compared to conventional topologies. As a result of this, the filter circuit’s size, cost, and complexity are considerably reduced. A modified sinusoidal pulse width modulator with a multicarrier phase disposition scheme is used to generate gate signals for 31-levels voltage at the output side. The modeling and analysis of the proposed MLI and PWM topology is conducted in Simulink environment, while hardware results authenticated the performance.