RTL to GDSII of Harvard Structure RISC Processor

This paper speaks about design of RISC processor and its implementation from RTL to GDSII. Verification of RISC processor Harvard structure is carried using Verilog (RTL file) and test bench for that Verilog file. Cadence NC Launch tool is used for simulation of code. Later verified Verilog file along with. sdc and .lib files, gate level net list was generated from cadence Genus tool. Till this part of gate level net list generations front end part of design will be carried out. Output of Genus tool are verified gate level net list file and. sdc constraints file. Pre-layout simulation results for power, area and timing are carried out. In backend design, cadence Innovus tool was used for floor planning, power planning and routing. Here also post layout simulations carried for power, timing and area. All these processes are carried out using 180nm technology cadence tool. The physical implementation of Harvard Structure RISC Processor is successfully implemented on Cadence Innovus tool. After carrying out pre-clock tree synthesis, post clock tree synthesis and post routing of circuit, one has obtained optimized results for timing 9.236ps, power 0.53155682W and area 17067.7584µm
²
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