Reduction of Timer Interrupts for Embedded Assembly Programs Based on Reduction of Interrupt Handler Executions

In the verification of programs for embedded systems, it is important to reduce the verification time. For this purpose, one solution is to reduce the number of interrupt handler executions. In particular, when periodic interrupts such as timer interrupts are incorporated, it is necessary to understand the actual time. In this paper, we propose an algorithm based on interrupt handler execution reduction (IHER) to reduce the number of timer interrupts by defining a CFA that can handle time, while considering real-time performance. The effectiveness of this algorithm is verified by a case study.