Failure Mechanism of Stress Migration in Via Sidewall for Dual Damascene Cu Interconnection

Generally, as devices scale, Cu metal is used more in the dual damascene process structure due to its better conductivity. TaN/Ta was often used because of better adhesion to Cu and SiO2, which are used as a barrier layer between IMD and Cu metal. SM is the phenomenon of metal void under tension of thermal stress. When the stress migration test (SM) was performed at three kinds of baking temperatures (150,200,250 °C ), it was only found that the minimum metal line width connected with the Via, SIV (stress induced voids) phenomenon will occur in via-1 sidewall at a temperature of 250°C.This paper will discuss the CDF plot results of SM and failure mechanisms, which were based on relative experiments such as via hole aspect ratio (AR) adjustment, Via bottom profile adjustment, SiCN remain thickness adjustment, polymer residue and barrier coverage improvement items.