Study of Layout effect on Gate oxide TDDB in sub-16nm FinFET technology

In this work, TDDB characteristic in sub-16nm FinFET technology are investigated by experiments. The Weibull slope β and voltage coefficient n of NMOSFET and PMOSFET are equals to 1.45/0.95 and -30.5/-37.6 based on the results having various stress voltage, respectively. Moreover, since the layout effect of NMOSFET and PMOSFET, the difference in T
63
normalized by total device gate oxide area are more than 4X and 2.5X. The dependence between Initial I
g
and T
bd
are studied, which shows that there is a negative correlation between initial Ig ratio and T
bd
ratio since difference of the equivalent gate oxide thickness E
ox
. Besides, mean E
ox
of 4Fins device is significantly larger than 2Fins device and 12Fins device based on the results of cumulative probability of the normalized initial I
g
, which results in the V
stress
gain of 4Fins device are equal to 88.5mV and 118.7mV for NMOSFET and PMOSFET, respectively.