Digital Calibration of 1.5 bits/stage Algorithmic ADC

This paper proposes a digital calibration technique for one stage algorithmic ADC implemented on a 1.5 bits/stage, 12 bits algorithmic ADC. The calibration algorithm accounts for capacitor mismatch, finite open-loop gain and offset voltage of the op-amp and parasitic capacitances. The proposed algorithm is used to calculate the calibration coefficients which are in turn used to calculate the weights with which output digital code of the algorithmic ADC are multiplied to obtain calibrated digital output. For 6% mismatch in capacitances in the ADC amplifier, the proposed calibration technique improved SNDR by around 23dB and SFDR by 28dB. The proposed algorithm has been extended to calibrate 2 stages cyclic ADC and the functionality of the calibration algorithm has been successfully validated.