Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse–Fine-control

Conventional digital low dropout regulator (DLDO) operating speed is invariable due to constant external reference clock. Fixed DLDO operating speed, regardless of the load state, cause inefficient power consumption for steady-state load or stability problem due to slow transient response time. This paper introduces DLDO with reference-less adaptive clock generation which is optimized by load states. Coarse-fine control and burst-mode are added to the shift register adjusting power transistors (PT) to achieve a fast transient response. The proposed DLDO is designed in 180nm BCDMOS and operates at 1.8V with an output voltage of 1.5V. The maximum and minimum operating frequency is 393MHz, 165MHz respectively. Settling time is 174ns at load current changes from 2mA to 10mA.