Low Energy and Error Resilient SOT-MRAM based FPGA LUT Cell

As process technology scales down, large standby power has become one of the critical issues for SRAM-based Lookup-Table (LUT). Recently, spin-orbit torque magnetic random access memory (SOT-MRAM) has become a promising candidate to replace SRAM based LUT. Thanks to its non-volatile characteristic, SOT-MRAM is expected to reduce power consumption. But, high write energy and read reliability issue are still large concern. In this paper, we propose a novel SOT-MRAM-based LUT cell using two transistors and a shared inverter. By removing cascading MUX from both read and write paths, we can reduce the write energy and improve the read reliability. HSPICE circuit simulations using the 65nm process show over 50 % of write energy savings compared to the state-of-the-art SOT-MRAM-based LUT.