A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL

A 7.68 GHz fast-lock digital multiplying delay-locked loop (MDLL) is presented. Implemented in a 40-nm 1.2-V CMOS process, the proposed MDLL achieves an output frequency of 7.68 GH with a high frequency multiplication factor N = 64. By adopting a cyclic Vernier TDC, the proposed MDLL achieves a fast lock time of 6 reference cycles. To reduce jitter integration caused by power supply noise, a differential pair based digitally controlled oscillator (DCO) is adopted. Also, to reduce deterministic jitter, a DSM-based dithering jitter reduction scheme has been adopted. The proposed MDLL achieves a simulated p-p jitter of about 16 ps at 7.68 GHz. It occupies an active area of 0.026 mm², and dissipates 29 mW at 7.68 GHz.