Recent Advances in Contact Resistance Improvement in Advanced Logic

Although pitch scaling has slowed down in recent logic CMOS generations, the demand for external and contact resistance reduction has only gone up. This can be understood by the fact that the transistor drive current densities have continued to increase, in part due to fin height scaling in advanced FinFET technologies [1] . This trend is likely to continue with the introduction of the Nanosheet device architecture as this device also utilizes effective device width scaling to help increase its drive current density [2] .