Layout Technique for Space Reduction of DC-Block Capacitors

This paper seeks to explore the channel performance and advantages of a new placement strategy for DC-Block capacitors that significantly reduces the board space required. In traditional capacitor placement there is no coupling between differential pairs, but there is a space requirement of approximately 1500mils x 800mils for implementation. A more compact cross-pattern design was developed which requires only 900mils x 100mils. This cross-pattern technique reduces the required board space by approximately 61%. Both placement techniques were simulated using the PCIE SeaSIM tool. The results revealed that overall channel-loss between both techniques remained constant, however in the cross-pattern method there was small eye degradation due to increased crosstalk in the channel. Ultimately, the cross-pattern technique proved to be an effective method of conserving board space while only presenting a minor degradation in channel performance.