Integrated circuit of clocked comparator for ultra-wideband radar

In this paper, the complete technological process of designing the integrated circuit (IC) from an idea to the working clocked comparator for the ultra-wideband (UWB) impulse radar device is proposed. Several IC technologies are investigated and the favourable is determined to design the radar receiver's clocked comparator. The clocked comparator circuit and its methodology are proposed to evaluate the performance within the simulation software. The IC layout is designed with pre and post-layout simulations. During the post-layout simulation, parasitics have been extracted to validate the performance of the device prior to manufacturing. An experimental setup is created to implement the IC into the UWB impulse radar for testing and measurements. The clocked comparator provides 9.1 GHz frequency bandwidth in pre-layout simulation and 5.6 GHz in post-layout simulation, while the manufactured prototype within the experimental setup provides 4 GHz bandwidth. The achieved results demonstrate that chosen technology allowed to design clocked comparator for the UWB impulse radar. Post-layout simulations empower the technology choice before manufacturing to reduce the costs of implementing other UWB radar blocks in one package, which would also reduce the overall size and improve the device parameters.