12-Bit 200 MS/s Switched-Current Pipelined Analog-to-Digital Converter for High-Speed DSL

This paper presents a 12-bit 200 MS/s switched-current (SI) pipelined analog-to-digital converter (ADC) for the receiver of the very-high-bit-rate digital subscriber line (VDSL), which is fabricated with TSMC 0.18-um 1P6M process. The proposed pipelined ADC is composed of ten 1.5-bit architecture with compensation circuit at the first ten stages and a 2-bit architecture at the last stage. In this study, a digital compensation circuit is used to eliminate the error generated by comparator and an active return current mirror is considered not only to reduce the input impedance but also to relax the channel-length modulation effect. Furthermore, a dummy switch is added to decrease the errors induced by the charge injection and clock feedthrough; and that a digital compensation circuit is redesigned to improve the digital codes by decreasing the signal delay. The simulation results showed that the differential nonlinearity (DNL), integral nonlinearity (INL), signal-to-noise-distortion ratio (SNDR), effective number of bits (ENOB), and power consumption was 0.405 LSB, 0.641 LSB, 69.87 dB, 11.324 bits, and 78.67 mW, respectively, at a supply voltage of 1.8 V with an input sine wave frequency of 5 MHz, an input current in the range of −40 to +40 μA, and a sampling rate of 200 MS/s.