12-Bit 200 MS/s Digital Transmitter for Very-High-Bit-Rate Digital Subscriber Loop

This paper presents a 12-bit 200-MS/s CMOS digital transmitter based on the requirement of very-high-bit-rate digital subscriber loop (VDSL). The entire architecture of the digital transmitter is composed of a digital-to-analog converter (DAC) and a fully differential current-mode line driver, which is fabricated in TSMC 90-nm 1P9M CMOS technology. The proposed 12-bit DAC is split into three stages. The first and second stages are a 6-bit sub-DAC and a 3-bit sub-DAC, which are implemented in thermometer code, and the last stage is a 3-bit sub-DAC, which is implemented in binary code for reducing the layout area and relaxes the circuit complexity. A small current source is used not only to isolate the output of digital circuit but also to reduce the current glitch. The DAC operates with a differential output current, which ranges from −4.095 mA to +4.095 mA, and its power consumption is about 5.0074 mW. The chip size is about 0.667 × 0.613 mm^2. Furthermore, an impedance synthesis is utilized to eliminate the matching resistor which works with extra power consumption. The capacitive feed-forward path is introduced to reduce the crossover distortion and to increase linearity. According to the simulated results, the output voltage of line driver is 4 V
PP
with a differential load of 100 Ω. The power consumption is about 5.4579 mW.