A Hardware Generator for Posit Arithmetic and its FPGA Prototyping

Posit arithmetic has better dynamic range and accuracy over the conventional IEEE-754 floating-point. In this paper, architectures for posit adder/subtractor and multiplier have been proposed that work as per the desired bit size of operands. Here, 16 and 32-bit architectures with different exponent size (ES) have been designed. FPGA implementations of these architectures have been done on the Xilinx Virtex-7 xc7vx330t-3ffg1157 device. In comparison with existing work, it has been observed that the usage of LUTs with ES=2 is lowered by 7.11/16.07% for 16/32-bit adders, and 1.81% for 32-bit multiplier with ES=3. In addition, 16/32-bit adder architectures require 31.47/31.66% lesser datapath delay. The 16/32-bit posit multipliers consume 10.40/10.84% lesser delay.