Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology

In this paper, we have designed and proposed a novel D flip-flop using Carbon Nanotube Field-Effect Transistor (CNTFETs). The proposed flip-flop operates on a True Single Phase Clock (TSPC) and is based on a master-slave TSPC latch in a cascaded configuration. The Proposed flip-flop has less Clock load i.e., only on two transistors. From the simulation results, we have observed that the proposed D flip-flop has less setup time (t
Setup
), hold time (t
hold
), clock to output propagation delay (t
Pc–q
), low clock load and low power consumption as well as low energy value compared to other existing flip-flops. The proposed D flip-flop consumes 99.98%, 99.89%, 36.8%, 99.6% low power and low energy compared to NAND based logic Flip-flop, Transmission gate logic based MUX Flip-flop, C
²
MOS Flip-flop, TSPC flip-flop respectively. Based on the simulated results, the proposed flip-flop is well suited for low power and energy efficient VLSI Systems.