Design Process of Optimal Dead-time for SiC MOSFET-Based Three-Phase Six-Switch Rectifier

This paper proposed a design process of optimal dead-time for the SiC MOSFET-based three-phase six-switch rectifier. The optimal dead-time is calculated by considering the parasitic capacitances and utilizing the charge concept. Experimental results demonstrate that the input current THD and power factor are improved by optimizing the dead-time. The efficiency is tested as 96.7 % at a 10 kW SiC MOSFET-based three-phase six-switch rectifier.