Quadrature Clock Generation Circuit for Time Interleaved Data Converters

The concept of time interleaving is commonly used for analog-to-digital (ADC) and digital-to-analog (DAC) converters addressing sampling rates beyond 100 GS/s. The presented circuit generates a four-phase clock signal, that supports fourfold time interleaved ADCs or DACs. With a frequency of 50 GHz an interleaved sampling rate of 200 GS/s is possible. The quadrature clock circuit exhibits amplitude imbalance below 0.9 dB and phase error below 4.9° in the frequency range from 37GHz to 50 GHz. The amplitude imbalance is the lowest, compared to other quadrature couplers.