Fast and Accurate Inductance Extraction for Power Module Layout Optimization Using Loop-Based Method

Electrical parasitics, especially parasitic inductance, play an essential role in enhancing power module design performance through reducing voltage overshoot and switching power losses. In this paper, a new electrical parasitic extraction model is developed, inspired by the loop-based extraction method from VLSI. This model shows only within 10% error compared to the FastHenry method while being orders of magnitude more efficient in run time and memory. For the same design, this method takes less than 0.5 seconds on the same machine to achieve similar accuracy. This method also significantly reduces the number of elements in the extracted netlist, which reduces the complexity for loop evaluation a few thousand times. Utilizing the divide-and-conquer strategy, this model demonstrates many advantages over previous work in layout optimization and post-layout simulation. The model is also attractive for use with optimization routines, and therefore has been used in the latest PowerSynth layout optimization tool.