Coding Schemes for Crossbar Resistive Memory with High Line Resistance in SCM Applications

Crossbar resistive memory with 1 Selector 1 Resistor (1S1R) structure is attractive for low-cost, power efficient, and high-density storage class memory (SCM) applications. As technology scales down to the single-nm regime, the increasing resistivity of wordline/bitline becomes a limiting factor to device reliability. Due to the line resistance, reliability of memory cells in an array is spatially non-uniform. In this paper, by mitigating and leveraging this spatial non-uniformity, we propose two simple yet effective coding schemes, one that utilizes interleaving and one that utilizes multiple codes based on a proposed location dependent code allocation (LDCA) framework, to reduce the undetected bit-error rate (UBER) or to allow for lower write voltage for power efficiency in the studied crossbar resistive memories.