Negative-Capacitance FETs for Advanced Nodes: Circuit Performance and Variability Analysis with Ferroelectric Dynamic Switching

In this paper, circuit benchmark of negative capacitance FinFET (NC-FinFET) are conducted using the in-house TCAD based on 7-nm and 14-nm FinFET technologies with high-κ dielectric replaced by ferroelectric material. The compact model is calibrated accordingly for circuit simulations. Compared with reference FinFET, NC-FinFET enables I
OFF
reduction and DIBL/SS/I
ON
enhancements. The results of ring oscillator (RO) analysis using the calibrated compact model suggest that 1) the ferroelectric (FE) dipole switching dynamics has negligible impact on the RO delay with the reported FE parameters, and 2) the NC-FinFET-based RO enables energy saving via V
DD
scaling at a fixed propagation delay. Finally, the impact of FE variability on transistor and circuit metrics is analyzed and found to be insignificant compared to other FinFET variation sources