Complementary FET for Advanced Technology Nodes: Where Does It Stand?

Nanosheet on nanosheet configured complementary FET (CFET) is investigated using the Materials to Systems Co-optimization (MSCO
^TM
) modeling framework at both device and circuit levels developed at Applied Materials. Compared to N3 FinFET with the same footprint for a single device, both nMOS and pMOS for CFET shows lower drive current than FinFET by 26% and 45% respectively. At the circuit level, CFET shows lower iso-power frequency by 20%, mainly due to lower drivability and high super-via resistance.