Implementation and Analysis of Efficient Low Power Dynamic Circuit Technique

Dynamic CMOS circuits offer numerous and essential applications, which drive their optimization to high-end performance. Also, the dynamic logic circuits are very efficient in terms of speed but at the same time these circuits suffer from high power consumption and noise. A high-speed circuit with low power consumption and good durability is now necessary due to recent research advancements. It has become vital to develop a novel circuit design to utilize the advantages of dynamic logic while addressing its disadvantages. The FSDPRO (Forced Stack with Diode PROfile) technique is used in this research to design a productive true single phase clock dynamic circuit. The proposed technique reduces the leakage power consumption in true single phase clock logic circuits based on stacking and low power diode transistors. To increase the charge storage and discharge at the dynamic node, two transistors are added between the logic transistors and the evaluation NMOS. To produce a stacking effect and reduce leakage power consumption, another NMOS transistor is inserted at the second stage dynamic inverter. The technique has been analysed for gates, flipflop and full adder circuits for both low (25°C) and high (110°C) temperature. Further an application of serial adder is also presented. The FSDPRO technique for AND2, OR2, OR4, D flipflop and 1-bit full adder circuits diminish active power dissipation of 49.6% to 99.6% and by 45% to 99.9% at low and high temperatures respectively. Further in case of idle mode for similar circuits, 5% to 70.8% and 4.9% to 27.6% reduction in leakage power consumption is detected with low and high inputs at 25°C and 110°C respectively.