A study and design of digital circuit

With the development of digital electronic technology and stricter social requirements, optimizing digital circuit systems has become a very important research direction or trend. More severe power consumption issues accompany the continuous development of integrated circuits. This paper mainly designs an A [79.02] FO4(1V), [90.247] Eu(1V),4-bit Absolute-Value Detector. And by changing the parameters of the device, we hope to get a practical delay power consumption improvement method. We have adopted the circuit style of serial adder + Comparator, static CMOS. In addition, we analyzed the delay and power consumption of the critical path and the non-critical path. First, we determine a voltage, and calculate the delay and power consumption. Then we change various circuit parameters and sacrifice the delay in exchange for better power consumption and performance. To calculate the delay of the main path of the circuit, and find the best proportion of the vdd and sizing to minimize the power consumption, within given delay constraint, we use it as a trade-off to minimize energy generated on the non-critical path and find the ratio of the gate sizing. It can make desired contributions to both energy minimization and delay increment. Through the research, we have designed a method to change the device's size in the circuit. This method can better reduce the power consumption of the circuit and has a certain optimization effect on the design of digital circuits.