Critical Technologies For Dynamic Comparator Design

This paper has reviewed some innovations to CMOS dynamic conventional comparator in recent years. In order to enhance the circuit performance of the comparator, the improved critical technologies of the comparator have been proposed, which made great efforts in optimizing low power consumption, high speed, low voltage, dynamic range, reliability, and low noise. The improvement has been made in the following aspects. Firstly, for the sake of optimizing the reset stage, the proposed comparator by Vijay Savani uses a new share charge transistor to balance the charge, and the proposed comparator by Subhash Chevella uses cross-coupled pairs to pre-charge. And then, for minimizing the delay, the proposed comparator by Siddharth adds N-parallel paths at output terminals, and the proposed comparator by Yao Wang adds an extra parallel connected positive feedback loop in two-stage latched comparator. Finally, so as to widen the input voltage, proposed comparator by Byung-Do Yang introduces an auxiliary amplifier at the output stage. The implementation results and methods of these innovations have been reviewed in this paper.