New Metric for Evaluating the Effectiveness of Redundancy in Fault-Tolerant Logic Circuits

Today, most of the methods for combinational circuits fault-tolerant design are based on the introduction of some structural redundancy, which provides more resistance to various destabilizing factors. Each of these methods provides means to synthesize circuits with different characteristics of reliability and redundancy, making their architecture more efficient for practical application in certain environmental conditions. In this regard, it becomes necessary to bring in some numerical estimate to determine the relevance of introducing additional structural redundancy into the device. In this paper, an efficiency metric is proposed, which helps to analyze protection method applied to a particular combinational circuit in terms of redundancy and fault tolerance. The main parameter for the presented function is the priority coefficient, which allows us to customize analysis with respect to main circuit characteristics that are in priority.