Area Efficient Hardware Architecture of Skeletonization for 2D Images

Thinning algorithms (TA) are commonly utilized to extract an object's functioning parameters. The skeletonization algorithm (SA) comprises of broad range of complex mathematics and involves lengthy implementations when dealing with real time (RT). Algorithms on hardware platforms can be applied to boost the efficiency of image processing applications. Reconfigurable equipment used as hardware module in the field of Field Programmable Gate Arrays (FPGAs) that can offer high performance with lower latency are being used for real world applications. FPGAs' inherent reprogramming capacity allows them application versatility while maintaining the efficiency benefits of a particular approach for an operation. Just real-time hardware devices can be used with fewer tools as in real-time implementations image sizes get larger. In the proposed architecture, the 8x8 image pixels are processed in one 3x3 window per clock cycle instead of one pixel per cycle. The proposed design shows significant reduction in area.