Design and verification of RISC-V CPU based on HLS and UVM

RISC-V is an open source instruction set architecture (ISA) based on the principles of Reduced Instruction Set Computing (RISC). High-level synthesis (HLS) can automatically synthesize high-level specifications (such as in C or C++) into low-level RTL specifications for efficient implementation in application-specific integrated circuits (ASIC) or field programmable gate arrays (FPGA). This article proposes a method to implement CPU based on HLS. Based on the RISC-V architecture, the processor is designed using C language and synthesized into RTL code through HLS. This method greatly improve the speed of design and reduce the manpower required for design. In addition, by using Universal Verification Methodology (UVM) to build a verification platform to verify the RTL code, the synthesized RTL code is reliably and fully verified.