Performance Analysis of CMOS, PTL and GDI Based Braun Multiplier for Signal Processing Applications

Power, speed and area are key design constraints in signal processing for computing applications as well as for handy electronic gadgets. Multiplier plays a significant role in energy efficient signal processing applications in digital systems. Product of large bit numbers occurs efficiently through binary multiplication. A low power and high speed Gate Diffusion Input (GDI) based Braun multiplier with improved row and column bypassing scheme is presented in this paper. From the simulated results, it is observed that, the GDI based Braun multiplier achieves energy savings more than 4% and up to 99% with CMOS and other methods and in the same way EDP savings more than 15% and up to 30% with CMOS and other methods by means of column and row bypassing techniques. From the layout, it is also analyzed that, GDI Braun multiplier is area efficient over CMOS and its other counter parts at the penalty of 9% more area in comparison with pass transistor logic (PTL) based column and row bypassing techniques.