A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks

The steadily increasing complexity of state-of-the-art designs requires enhanced capabilities for post-silicon test and debug. By this, the demands concerning the quality as well as the diagnostic capability are met. Several sophisticated techniques have been proposed in the past to address these new challenges. However, these techniques heavily enlarge the on-chip generated data that has to be stored in rarely available and highly expensive memory and, especially, to be transferred via a low-speed interface. Thus, applying data compression is a highly beneficial objective to reduce the dedicated on-chip memory and the required transfer time. This work proposes a novel compression technique, which significantly reduces the volume of on-chip generated debug data by orchestrating a deliberately parameterized two-stage neural network. More precisely, a codeword-based compression procedure is realized, which can be directly implemented in hardware and, hence, be seamlessly integrated into an existing test/debug infrastructure. So far, it has not been possible to realize such compression by classical (algorithmic) approaches allocating only reasonable hardware resources. The experimental evaluation validates that the proposed scheme achieves similar results as the off-chip codeword-based approach being applied for incoming test data.