Research on Power Device Structure Based on FO Package Method

Most of the existing power chips are connected by wire bonding or copper sheet welding. With the development of high performance, small size, modularity and high power density of power devices, the packaging method starts to develop towards FO(Fan-out)-based packaging technology. This scheme can be designed with complex line layout and flexible metal shape linkage method. And it is a high efficiency package method with low parasitic capacitance, inductance, very low
${\mathrm{R}_{\text{dson}}}$
and excellent heat dissipation at high frequency. The thermal stress problem in reflow soldering is a key research object in device development, and this paper mainly focuses on the research of DFN3030 product structure based on FO package thermal stress. Using finite element software to establish a three-dimensional model, the main factors affecting the metal shape of the chip surface, copper thickness, and plastic sealing material thickness are simulated and analyzed. The simulation is used to determine the relationship between different factors affecting thermal stress, and two different structural solutions are selected for sample verification to confirm whether the simulation structure matches the actual product result trend. Through the actual product reliability verification, it is confirmed that the thermal stress trend of the actual product matches with the theoretical results. And through the sample verification, the product with FO package DFN3030 meets the reliability requirements of MSL3, TC 500cycles@(-55~125 °C), PCT 96H@(120 °C, 100%RH), HTSL 1000H@150°C, THB 1000H@(85 °C, 85%RH).