A Parallel Decision Feedback Equalizer Structure For Terahertz High-speed Communication System

The purpose of this paper is to propose a new structure for LMS equalization using parallel decision feedback equalizer (DFE) to achieving 20Gbps communication capacity. The structure is implemented on the Xilinx XCKU115-FLVD1924 FPGA chip. In order to achieve 20Gbps capacity, 16QAM signal and 156.25MHz clock frequency is applied. This scheme contributes a new parallel signal processing realization for high speed wireless signal processing in FPGA.