Reduced Power Combinational Logics in 16nm CMOS Technology

This paper presents a 3-bit NOR gate and a Differential Cascode Voltage Switch Logic (DCVSL) with improved power in 16nm cmos design. The proposed designs use two values of threshold voltage as well as two values of oxide thickness. Static power, delay and power-delay-product of new designs are compared with circuits used for low power and high performance applications. It is found that there is a significant improvement in static power of upto 99.9% in the proposed designs. There is a little reduction in the performance of the designs without any area overhead.