Analysis of Energy-Delay-Product of a 3D Vertical Nanowire FET Technology

To sustain transistor scaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) are a promising alternative. This work analyses the energy-delay-product (EDP) for a junction-less 3D vertical gate-all-around nanowire FET technology, with a physical channel length of 14nm. Comparisons with the EDP of a baseline 7nm FinFET technology are carried out. The analysis motivates a new 3D neural network compute cube (N
²
C
²
) concept. Our results show that a 10x gain in EDP can be achieved for a physical VNWFET gate length of 14nm.