Improving Power Supply Induced Jitter Simulation Accuracy for IBIS Model

This work presents a new algorithm for improving the simulation accuracy of power supply induced jitter (PSIJ) in input/output buffer specification (IBIS) model. The improvement is realized by modifying the switching coefficient K
u
and K
d
as a function of both time and power rail voltage. The incorporation of time averaged effect of the power rail noise on buffer output switching edge during the time range of buffer propagation delay is the key element for the enhanced accuracy. In addition, implementation of the proposed algorithm in an open source spice simulator Ngspice is demonstrated. The accuracy of the proposed new algorithm is validated through transistor level circuit simulations.