Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable Prefetcher

Computer architects need to choose the design configurations which will work effectively across most commonly used workloads. Design space exploration of caches enables the architect to choose the right configuration based on metrics such as hit rates, power, area, and timing. Although the idea of a cache simulator is not new, the hardware/FPGA implementation of such simulators has not been well explored. We implement an FPGA accelerated parameterized two-level cache simulator called Cache-accel which can be partially reconfigured to include prefetching. The key motivation behind the idea is the speed with which the design space exploration can be carried out by exploiting the parallelism available in an FPGA. Cache-accel reports cache metrics such as hit/miss rates with and without prefetching for nine cache configurations in parallel. We run a set of SPEC 2017 benchmarks on Cache-accel and find that it can run nearly 7x and 11.5x faster (on an average) as compared to ChampSim and Snipersim to generate hit/miss rates for the nine parallel configurations.