16-bit Modified Vedic Paravartya Divider with quotient in fractions

High Speed DSP applications are influenced by the efficiency of the arithmetic modules used. Division is a bulky and computational complex operation with high latency than the other arithmetic operations. Vedic Mathematics provides a better method of computation as they are based on the principles on which the human mind works. In this paper, a new scalable architecture for Paravartya division have been proposed in which 8 partial quotient terms are generated parallelly in each stage and produces a quotient that is accurate upto one decimal place. A 16-bit by 16-bit divider based on this architecture is found to be 4.5ns faster than the conventional serial implementation of Paravartya sutra. It is also found to have 62 percent reduction in delay when compared with the existing dividers like SRT, Newton-Raphson and Nikhilam dividers that produces quotient and remainder.