Synthesis of Quasi Delay Insensitive Asynchronous State Machines from Synchronous Specifications

Nowadays, ultra-low-power projects of digital circuits have become a priority. One technique that allows a strong reduction in power consumption of the circuit is the sub-threshold voltage operation, but it leads to some drawbacks. The Quasi Delay-Insensitive (QDI) asynchronous circuits tend to consume less energy. They are modular and robust to temperature variations, delay, noise, and have low electromagnetic emission, so they prove to be an attractive solution to operate at sub-threshold voltage. In this paper, we propose an architecture and approach that synthesizes asynchronous finite state machines (AFSM), in the QDI class. Conventional synchronous specifications describe them, and synthetized QDI_AFSMs can operate within sub-threshold voltage. Three benchmarks were prototyped in FPGA in the five main architectures, where the proposed architecture achieved an average reduction of 17.5%, 25.8%, 33.5%, and 26.0%, respectively, in latency time, LUTs (area), dynamic power and static power.