Comprehensive In-field Memory Self-Test and ECC Self-Checker -Minimal Hardware Solution for FuSa

As technology advances and System on Chip (SoC) become more complex, more and more embedded memories are packed inside the SoCs to cater the system requirements. Probability of malfunctioning of the device infield due to soft or hard defects in these memories and associated circuitry increase proportionally as well. As a result, in addition to testing and screening the product during manufacturing stage, the need for in-field testing of the memories has become critical to address Functional Safety (FuSa) requirements in mission critical industries such as automotive, medical and Artificial Intelligence (AI). In general, on most SoCs, Error Correcting Code (ECC) or parity checking schemes are implemented to detect and correct the error during memory access. Ensuring the correctness of the ECC operation in-field is also a safety critical requirement. This paper describes the methodology adopted for testing of embedded memories in safety critical SoCs and to verify the ECC logic in-filed with minimal hardware. In this proposed methodology, hardware and software system infrastructure is developed around industry standard memory test embedded instruments (Memory Built-In Self-Test controller and associated logic) to enable memory self-test and ECC logic testing during in-field usage. This paper describes the methodology adopted for testing of embedded memories in safety critical SoCs and to verify the ECC logic in-filed with minimal hardware. In this proposed methodology, hardware and software system infrastructure is developed around industry standard memory test embedded instruments (Memory Built-In Self- Test controller and associated logic) to enable memory self-test and ECC logic testing during in-field usage.

I. Introduction

Functional Safety (FuSa) is becoming a critical issue for industrial and automotive chips. IEC61508 and ISO 26262 are industry standards for functional safety in industrial and automotive domains respectively. These standards address possible hazards caused by malfunctioning behavior of electrical or electronic devices due to random hardware failures and systematic failures. SoC can be FuSa compliant by implementing identified safety measures through hardware, firmware and/or software to address necessary requirements. As per standard, FuSa basically has three metric requirements [1]: •

SPFM = (Single point fault metric): It is the percentage of failures originating from single point faults that are detected.

•

LFM = (Latent fault metric): It is the percentage of failures caused by multiple undetected faults which are covered by safety measures.

•

PMHF Metric for random Hardware Failures) related to both SPFM & LFM. In fact, the latent faults are also contributing (by means of a complicated formula) to the overall PMHF.