Designing of Adiabatic Approach for Power Efficient Full Adder Circuits

In the recent development of VLSI technologies, the most important difficult case is complexity in power dissipation and heat removal process due to the increasing number of gates per chip. As a result, one of the critical issues in the design of low power VLSI circuits is power dissipation. Adiabatic logic is a promising technique for achieving high performance while limiting the power dissipation in low power VLSI circuits. Self-repairing designs with complete fault coverage are required for industrial applications because it will destroy the arithmetic circuit function. The Self repairing full adder circuit using Efficient Charge Recovery Logic (ECRL) and Positive Feedback Adiabatic Logic (PFAL) has been proposed in this paper. Compared to the existing technique, the proposed full adder circuit consumes almost 30% less power systems and 56% more speed. Compared to the existing system with various design models, the proposed adiabatic logic (PFAL) based low power Self repairing full adder designed by connecting the two XNOR gates act as primary inputs to the sum and carry output of the proposed full adder while a faulty sum and carry is given to the secondary inputs consumes extremely low power and operates at high speed. The proposed Self repairing circuit detects the fault with low power consumption in complex circuits. Proposed structure consumes lower area overhead relative to the traditional self-repairing circuit.